`timescale 1ns/1ps
`default_nettype none
module alu(
    input  wire [31:0] a,
    input  wire [31:0] b,
    input  wire [3:0]  alu_ctrl,  // 0000:ADD, 0001:SUB
    output reg  [31:0] y
);
    always @* begin
        case (alu_ctrl)
            4'b0000: y = a + b; // ADD / ADDI
            4'b0001: y = a - b;   // SUB
            default: y = 32'b0;
        endcase
    end
endmodule

